The semiconductor device industry has a market driven need to reduce the time required for function and speed testing of integrated circuits (ICs), in particular during the function testing of IC die on semiconductor wafers at the end of the fabrication process, which may be known as wafer probe, or simply known as probe. A reduction in testing time will result in a reduction in overall device cost, in particular for the high number of relatively low cost memory chips used in virtually every electronic device, since the cost of testing may be a relatively larger portion of the total IC cost in such low priced devices. Since each individual memory chip may be relatively low priced, and because of the large number of individual memory chips that may be used in any single electronic device, even a small reduction in overall memory chip cost may have a large impact on the cost of an electronic device, such as a personal computer.
It is known to electrically test individual IC die at wafer probe with automated test equipment (ATE), which is basically a computer which can electrically drive some or all of the input/output (I/O) pads on the die. Using ATE, it is possible to determine if the application of a particular input vector (i.e., the voltage levels on all of the I/O pads being driven at that moment) results in the correct output vector. A probe test may contain a large number of different input vectors to test as many possible configurations of the die as economically feasible. The interface connecting the ATE to the die is a series of springy wires (probes) arranged on a printed circuit card to contact the die I/O pads.
One method of reducing IC cost is to reduce the amount of time required to test each of the individual memory chips at wafer probe by testing more than a single IC die at a time, using the available number of parallel data paths on a particular testing machine. Clearly, testing two forty pin IC die in parallel would cut the testing time in half, and thus cut testing cost significantly, assuming that the particular testing system has at least eighty parallel data paths. An additional issue is that the interface between the testing system and the IC die, known as a probe card, will have to have twice as many individual electrical contact wires, known as probes, arranged to form two probing sites, one for each of the two IC die that will be tested in parallel. A further issue is that a probe card designed to test more than a single die at a time clearly has to be moved differently than in the previous case of single IC die testing, where the probe card is simply moved to each die in turn.
It is known that each time the wires of a probe site are set down on the input/output (I/O) pads of an IC die (known as a touchdown), there is potential damage to the die, resulting in a potentially defective die after assembly into a package, and thus it is desired that each individual die be contacted by a probe site only a single time, or at least as infrequently as possible. This is easy to do in the previously noted case of testing a single die at a time. In addition, there is a possibility of the wires of the probe site being damaged each time the probe site contacts the I/O pads of an IC die, or the edge of the wafer. Thus, the movement of a multiple die site testing probe card is desirably calculated to minimize the number of times a probe site touches down on incomplete IC die near the edge of a semiconductor wafer.
It is desirable to have the multiple probe site tester card contain as many probe sites as the ATE system can handle in parallel, since this reduces the number of times that the card needs to be moved in relation to the wafer (or equivalently, the wafer moved in relation to the card) to test all of the die on a wafer, and thus may reduce the total testing time. For example, if an ATE has 500 potential parallel data channels, then a 40 pin IC die might be testable in groups of 12 die at a time, using 12 contactor probe sites. It is unlikely that there would be a case where less than all possible die are tested on a wafer, but the invention is not so limited.
Two problems must be solved simultaneously to obtain the various results discussed. First, the contactor configuration must be determined consistent with the maximum number of die that can be tested simultaneously with the ATE being used, and with the locations of the potentially good die on the wafer to be probed. Second, the locations that the probe card will touchdown on the wafer, and the order in which they will be contacted, needs to be determined. These two problems are interrelated and need to be solved together, with additional concern given to the number of die that may be contacted more than once. For example, if the probe card is limited to testing only 12 die at a time, as in the last example, then a wafer having 600 potentially good die will have at least 50 touchdowns, assuming that the pattern of the 12 probe sites, (i.e., the contactor configuration) is arranged so that there are no die that are probed more than once, and that there are no probe sites that ever are positioned over a die that is too close to the edge of the circular wafer to ever be potentially good.
Designing a contactor configuration that meets the needs of testing essentially all potentially good die on a wafer under test, testing as many die simultaneously as the ATE system allows, while not contacting a single die more than once, and minimizing the number of touchdowns on a wafer may not be difficult in cases where the number of die on a wafer is low, but it rapidly becomes difficult when the number of contactors on a probe card increases, as has occurred with newer more capable ATE systems, and as the number of die on a wafer increases, as has occurred with increased miniaturization and larger wafer size.
A method is needed to design semiconductor probe cards having the optimum number and placement of die probe sites for function testing integrated circuit (IC) die in parallel (i.e., testing more than a single die at a time) at wafer probe test, while minimizing the number of times the probe card must be moved to test all the IC die on a semiconductor wafer, as well as minimizing the number of individual IC die on the wafer that are probed more than once during the wafer test. With such an arrangement, the amount of testing time at wafer probe may be reduced in proportion to the number of IC chip tested in parallel.